AMD Ryzen I am getting it!!!!

[Powpow]

I do not think there is any issue. AMD marketed this as a mainstream workstation CPU and they delivered just that.

There are issues mentioned as you can clearly see in all the youtube videos posted in this thread since release, but nothing that can't be fixed once the board partners figure out how to optimize for this new architecture and get more time to actually do so.

I think there is an issue just that it is very small and expected with a new processor much less a new architecture. Nothing that should prevent someone from buying it. By the time BIOS and micro code is upgraded we will be even more impressed by Ryzen.

AMD has always been engineers at heart and this platform is set improve with age just like their GPUs. The AM4 platform is good for the next 4 years and all processors released in the future should work with motherboards released today.

Trust me this is good for more than 4 years as I have a 5 year old quad core processor that I recently overclocked and Jah know does it still perform like a dream. So having 16 threads that can run up to 4ghz and still keep at a decent temperature, should be good for another 10 years the least.

[topanaris]

Why does this crap always happen to AMD. Companies by and large will have their respective issues at lauch, but ,relative to Intel in the CPU space; AMD just cant seem to buy a break. The power draw RX480 issue is still fresh in my mind. Provided that they can fix all of this by closer collarboration with the respective board partners and companies I see this as a none-issue. However, shareholders might not agree. Simple reason more people will be buying this for gaming than productivity.

[crosswire]

https://msdn.microsoft.com/en-us/lib...(v=vs.85).aspx

A multitasking operating system divides the available processor time among the processes or threads that need it. The system is designed for preemptive multitasking; it allocates a processor time slice to each thread it executes. The currently executing thread is suspended when its time slice elapses, allowing another thread to run. When the system switches from one thread to another, it saves the context of the preempted thread and restores the saved context of the next thread in the queue.
The length of the time slice depends on the operating system and the processor.

I am suspecting some tweaking is needed in Windows to get the processor utilization up to 90+.

Has anyone ever saw less than 90+ CPU core utilization when writing a demanding CPU app on windows.

I don't see Ryzen specs (cache/registers/etc) being less than the previous FX architecture, so I do not suspect a hardware glitch.

I wonder how a DOS OS or linux would perform in benches.

[delimedz]

R5 launching april11. more benchmarks incoming

[crosswire]

https://community.amd.com/community/...mmunity-update


Thread Scheduling

We have investigated reports alleging incorrect thread scheduling on the AMD Ryzen™ processor. Based on our findings, AMD believes that the Windows® 10 thread scheduler is operating properly for “Zen,” and we do not presently believe there is an issue with the scheduler adversely utilizing the logical and physical configurations of the architecture.

As an extension of this investigation, we have also reviewed topology logs generated by the Sysinternals Coreinfo utility. We have determined that an outdated version of the application was responsible for originating the incorrect topology data that has been widely reported in the media. Coreinfo v3.31 (or later) will produce the correct results.

Finally, we have reviewed the limited available evidence concerning performance deltas between Windows® 7 and Windows® 10 on the AMD Ryzen™ CPU. We do not believe there is an issue with scheduling differences between the two versions of Windows. Any differences in performance can be more likely attributed to software architecture differences between these OSes.

Going forward, our analysis highlights that there are many applications that already make good use of the cores and threads in Ryzen, and there are other applications that can better utilize the topology and capabilities of our new CPU with some targeted optimizations. These opportunities are already being actively worked via the AMD Ryzen™ dev kit program that has sampled 300+ systems worldwide.

Above all, we would like to thank the community for their efforts to understand the Ryzen processor and reporting their findings. The software/hardware relationship is a complex one, with additional layers of nuance when preexisting software is exposed to an all-new architecture. We are already finding many small changes that can improve the Ryzen performance in certain applications, and we are optimistic that these will result in beneficial optimizations for current and future applications.

Temperature Reporting

The primary temperature reporting sensor of the AMD Ryzen™ processor is a sensor called “T Control,” or tCTL for short. The tCTL sensor is derived from the junction (Tj) temperature—the interface point between the die and heatspreader—but it may be offset on certain CPU models so that all models on the AM4 Platform have the same maximum tCTL value. This approach ensures that all AMD Ryzen™ processors have a consistent fan policy.

Specifically, the AMD Ryzen™ 7 1700X and 1800X carry a +20°C offset between the tCTL° (reported) temperature and the actual Tj° temperature. In the short term, users of the AMD Ryzen™ 1700X and 1800X can simply subtract 20°C to determine the true junction temperature of their processor. No arithmetic is required for the Ryzen 7 1700. Long term, we expect temperature monitoring software to better understand our tCTL offsets to report the junction temperature automatically.

Simultaneous Multi-threading (SMT)

Finally, we have investigated reports of instances where SMT is producing reduced performance in a handful of games. Based on our characterization of game workloads, it is our expectation that gaming applications should generally see a neutral/positive benefit from SMT. We see this neutral/positive behavior in a wide range of titles, including: Arma® 3, Battlefield™ 1, Mafia™ III, Watch Dogs™ 2, Sid Meier’s Civilization® VI, For Honor™, Hitman™, Mirror’s Edge™ Catalyst and The Division™. Independent 3rd-party analyses have corroborated these findings.

For the remaining outliers, AMD again sees multiple opportunities within the codebases of specific applications to improve how this software addresses the “Zen” architecture. We have already identified some simple changes that can improve a game’s understanding of the "Zen" core/cache topology, and we intend to provide a status update to the community when they are ready.

As a learning game developer, I am interested in finding how to maximize the potential of affordable gaming CPUs.

How to hit 90+ CPU utilization in multi-threaded apps, in as much cores as possible, and definitely in at least 1 of the cores.

Common sense would be to give critical threaded in the app the highest priority (analogous to critical path in project management). Then the OS should take care of the rest. The OS, when switching from a critical thread, should store its thread data as close as possible to the cpu pipe, because it is a critical thread. For low priority threads, it should not matter where it is save).

Also, if the app does not expect to read or write to a critical thread, in 2 or 3 time slices, then that thread should be tag it if possible, so that it does not need to be offloaded, if possible, for those time slice. All the OS needs to do is to let it run and check "if completed" provided I have multiple cores to carry out other critical threads by the OS.

Critical threads and helper threads should be distributed among-st the core complexes. For example, if I have 2 complexes and 2 critical threads, then each critical thread should be on its own complex, so that the L1 cache or whatever is better utilized, as opposed to having the L1 cache or whatever of one complex being competed for by 2 critical threads.

The helper threads should also be on the same complex. For example, if helper thread h1 provides data to critical thread c1 and if helper thread h2 provides data to critical thread c2, then it would be unwise to run (via time slice switching) h1 and c2 together on the same complex and c2 and h1 on another complex, because in the end data would have to be read unnecessarily between complex and all the cpu pipes will be idle while waiting for data, and not even 1 cpu core pipe will hit 90+ utilization. The OS may be able to sense which threads are providing data to which threads, and schedule accordingly.

This is my view or opinion.

I will continue researching.

[crosswire]

Lisa Su has said that AMD was working with developers.
http://video.cnbc.com/gallery/?video=3000598204
March 3, 2017

It seems like there is indeed much optimization moving forward, in how developers code apps.


I am curious to know what type of dev optimizations are being done.

[crosswire]

Adding this video because it explains the cache architecture a bit.

https://www.youtube.com/watch?v=m1amGwPnUuA

It was wise and cost effective of AMD to have a 4 cores in the CCX (CPU-Complex), so that you can have 8 cores and 4 cores processors. The 4 core user do not have to pay the cost of 8 cores as there is no 8 cores built into one CCX, its just 4 cores in the complex, and thus you pay for one complex. Furthermore, defective dual CCX can easily lead to 6 core variants, and defective single CCX can lead to 2 core variants. Less is wasted.

Ryzen 5 quad core is likely to be 1 CCX.

I don't know for sure if Ryzen 5 will be better at gaming. (See video above)

Some details on Zen
https://en.wikichip.org/wiki/amd/microarchitectures/zen
This is definitely new

CPU Complex (CCX)
AMD organized Zen in groups of cores called a CPU Complex (CCX). Each CCX consists of four cores connected to an L3 cache. The L3 cache is an 8 MiB 16-way set associative victim cache and is mostly exclusive of the L2. The L3 cache is made of four slices (providing 2 MiB L3 slice/core) organized by low-order address interleaved. Every core can access every L3 cache slice with the same average latency. When a certain core starts working on a chunk of memory it will fill up the L2 and as it continue to execute and fetch new data any spillover will find its way in the L3.

Depending on the exact processor model, an 8-core processor will incorporate two CPU Complexes. It's important to note that the L3 in Zen is not a true last level cache (LLC) as the 16 MiB L3$ will consist of two separate 8 MiB and not one unified L3. While no details have yet been disclosed, AMD did state that the separate complexes can communicate with each other via their custom fabric which connects the CCXs along with the memory controller and I/O. This design choice is aligned with the AMD's goal of scaling up to large high-performance multi-core system (i.e., high scalability, particularly in the server segment, through high core count and large bandwidth) but it does mean that systems making use of Zen processors have to treat every CPU Complex as a processor of its own - i.e., schedule tasks using cache-coherent non-uniform memory access (ccNUMA-aware) scheduling. This is important to ensure that threads are not moved from one CCX to the other as doing so will likely incur unnecessary performance penalties (as cache data would need to be communicated over via the fabric from one CCX to the next which has additional overhead latency and lower bandwidth).

Zen has some new instructions
https://en.wikichip.org/wiki/amd/mic...w_instructions

So far, only Windows 10 has support for Zen. It could be just preliminary data.
https://en.wikichip.org/wiki/amd/mic...#Compatibility

[BNOVA]

Lisa Su has said that AMD was working with developers.
http://video.cnbc.com/gallery/?video=3000598204
March 3, 2017

It seems like there is indeed much optimization moving forward, in how developers code apps.


I am curious to know what type of dev optimizations are being done.

Interesting observation. I am looking forward to Ryzen 5 reviews as well.

So far, only Windows 10 has support for Zen. It could be just preliminary data.
https://en.wikichip.org/wiki/amd/mic...#Compatibility

Microsoft always stated that they will not support any new CPUs on older software (Windows 7 etc..) and AMD will only release certified drivers for Zen on Windows 10 or newer. However the CPU will work on Windows 7, it just that the new instruction sets will not be supported on it. So if a someone has problems at the software level that is caused buy using Zen on Windows 7 , 8 or 8.1, Microsoft will not offer support for it.

[crosswire]

Rubbish!!

It was wise and cost effective of AMD to have a 4 cores in the CCX (CPU-Complex), so that you can have 8 cores and 4 cores processors. The 4 core user do not have to pay the cost of 8 cores as there is no 8 cores built into one CCX, its just 4 cores in the complex, and thus you pay for one complex. Furthermore, defective dual CCX can easily lead to 6 core variants, and defective single CCX can lead to 2 core variants. Less is wasted.

Ryzen 5 quad core is likely to be 1 CCX.

Ryzen 5 quad core may be a 2 CCX die derivitive with 2 cores disabled on each CCX.

[pezz]

Gaming test.


Power consumption while gaming


https://www.techpowerup.com/reviews/..._1800X/13.html